4.8.2. Function and operation of module

This example module contains four 32-bit wide registers, which can be accessed using byte, halfword or word, read or write transfers. Extra read only locations are provided that generate logical combinations of these four registers. The module memory map in Table 4.9 shows the logical functions that the slave can provide, and the addresses at which the functions and four read/write registers are accessed.

Table 4.9.  Memory map of the example AHB retry slave

Address

Read location

Write location

0x00

R0

R0

0x04

R1

R1

0x08

R2

R2

0x0C

R3

R3

0x10

Not R0

-

0x14

R0 and R1

-

0x18

R1 or R2

-

0x1C

R2 xor R3

-

0x20

R0 and R1

and R2 and R3

-

0x24

R0 or R1

or R2 or R3

-

0x28

R0 xor R1

xor R2 xor R3

-

All addresses shown in the memory map are offsets from the module base address. In the default system the retry slave module occupies memory locations 0x40000000 to 0x5FFFFFFF.

When any of the memory locations are accessed, the high order address lines are used to determine the response that the slave provides, inserting wait states or retry cycles.

The address lines that are used are:

The number of wait states inserted for each read or write module access can be varied from 0 to 15, and the number of times the slave provides a retry response can be varied from 0 to 3.

When the slave is programmed to provide a retry response, the number of wait states to insert must be set to a value greater than zero, because all retry responses require two cycles, with a wait state inserted during the first cycle.

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