4.8.3. System description

The following paragraphs give a description of how the HDL code for the example retry slave is set out. A basic block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs and outputs used in the system. This part should be read together with the HDL code.

Figure 4.31 shows a basic block diagram of the retry slave module system.

Figure 4.31. Retry slave module block diagram

The retry slave comprises a set of read/write registers, and programmable wait/retry generation logic.

All registers used in the system are clocked from the rising edge of the system clock HCLK, and use the asynchronous reset HRESETn.

Figure 4.32 shows the retry slave HDL file.

Figure 4.32. Retry slave module system diagram

The main sections in this module are explained in the following paragraphs:

AHB slave bus interface

This module uses the standard AHB slave bus interface, which comprises the valid transfer detection logic, and the address and control registers, which are used to store the information from the address phase of the transfer for use in the data phase.

Write data mask

The amount of data written to the four internal registers depends on the transfer size setting. The mask is used to control which bytes of data are written to the 32-bit registers, and which bytes are left unchanged. A single mask value is used to allow one set of size decoding logic to be used for all registers in the module, rather than having a set of decoding logic for each register.

The bytes of data that change are set LOW in the mask, and all other bits are set HIGH.

Read/write registers

Four 32-bit registers are used to store user data, all initializing to zero. They are only enabled when addressed during a write transfer, and when any wait states or retry cycles have ended. The data mask is used to control writes of byte, halfword and word, by masking out the bits of the current write data that are not needed, and ORing it with a masked version of the current register data. This ensures that only the required bytes of the read data are used, and the unchanged register bytes are reloaded with the previous register value.

Response generation logic

This logic is used to control the generation of wait states and retry cycles.

Wait states are inserted when the address of the current transfer has a nonzero value in bits [11:8]. This value, from zero to fifteen, is loaded into the CurrentWait register, and then decremented each clock cycle until zero is reached. This counter value is used to hold the HREADYout output LOW until zero is reached, when HREADYout is set HIGH and the transfer can complete.

Retry cycles are inserted when the address of the current transfer has a nonzero value in bits [13:12] and [11:8], because all retry cycles require at least one wait state. This value is loaded into the CurrentRetry register, and is decremented each time the transfer is retried until zero is reached. The input to the iHRESP register is set according to the state of the retry logic and the wait logic, so that if more than one wait state is inserted, the HRESP output only changes during the last HREADY LOW cycle. Retry responses are generated until the counter reaches zero, when the HRESP output indicates that the transfer can complete normally.

Read data generation

Different read data values must be generated according to the address of the current transfer, selecting output data from one of the four registers or one of the seven combinational outputs. This section of the code selects a data source during the data phase of a valid transfer, and then directly drives the output data bus HRDATA with this selected data value.

This combinational output path allows a zero wait state response to be possible, because data written to a register can be read the following cycle with a zero wait state transfer. If a registered output data path is used, reads from registers that were written to in the previous cycle must have at least one wait state inserted, to allow for the internal data register to sample the write data, and then for the data register output to be sampled by the output read data register, before being driven onto the output read data bus.

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