4.9.1. Signal descriptions

Table 4‑7 describes the signals used by the SMI.

Table 4.10. Signal descriptions

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HADDR[31:0]

Address bus

Input

The 32-bit system address bus.

HTRANS[1:0]

Transfer type

Input

This indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HWRITE

Transfer direction

Input

When HIGH this signal indicates a write transfer, and when LOW, a read transfer.

HSIZE[2:0]

Transfer size

Input

Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The protocol allows for larger transfer sizes up to a maximum of 1024 bits.

HWDATAin[31:0

Write data bus

Input

The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended, however, this can easily be extended to allow for higher bandwidth operation.

HSELExtMem

Slave select

Input

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is a combinatorial decode of the address bus.

HRDATAin[31:0] HRDATAout[31:0]

Read data bus

Input/output

The read data bus is used to transfer data from bus slaves to the bus master during read operations. A minimum data bus width of 32 bits is recommended, however this can easily be extended to allow for higher bandwidth operation.

HREADYin

HREADYout

Transfer done

Input/output

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESP[1:0]

Transfer response

Output

The transfer response provides additional information on the status of a transfer. This module always generates the OKAY response.

Remap

Reset memory map

Input

When LOW, the internal memory is not part of the system memory map, and external memory is mapped from address 0x00000000, which normally contains the system startup code. In normal operation this signal is HIGH, allowing use of the internal memory.

TicRead

Drive out read data

Input

This signal controls the SMI to drive the current read data from HRDATA to XD.

XD[31:0]

External data bus

Input/output

This is the bidirectional external data bus. In normal operation it is driven by the external bus when XOEN is LOW, and by this module when XOEN is HIGH. During system test this becomes the test bus TESTBUS and its direction is controlled by the TIC control signals.

XA[30:0]

External address bus

Output

The external address bus becomes valid during the HCLK LOW phase of the transfer and remains valid throughout the rest of the transfer.

XCSN[3:0]

External chip select

Output

These signals are active LOW chip enables for each of the three banks (0-1, 3) of static memory. XCSN[3] must be connected to the memory containing the startup program (boot ROM/BIOS) for the system.

XOEN

External output enable

Output

This is the output enable for devices on the external bus. This is LOW during reads from external memory, during which time the selected bank must drive the XD bus.

XWEN[3:0]

External write enable

Output

This is the active LOW memory write enable. For little-endian systems, XWEN[0] controls writes to the least significant byte and XWEN[3], the most significant. The example system is configured to be little-endian. The SMI is configured to have a minimum of two wait states when writing to memory. XWEN is only valid during the second cycle of the write transfer.

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