4.9.2. Functional description of the SMI

The SMI has five functions in the example system described in the following paragraphs:

External bus control

To perform a read from external memory, XOEN must be LOW and the XD output is tristated, allowing it to be driven with read data by the external memory.

Figure 4.34 shows the timing of a read from memory with zero wait states.

Figure 4.34. Zero wait memory read

Note

The data must be valid on the XD bus in time for the signal to propagate on-chip so that the HRDATA bus becomes valid before the next rising edge of HCLK. If this setup time cannot be achieved, the access requires wait states.

To perform a write to the external memory, XOEN must be HIGH, to allow XD to be driven by the SMI with a registered version of HWDATA.

The SMI requires at least two wait states to be added for a write to memory, to allow for the timing of the XWEN write enable signal relative to the XA and XD buses. When XWEN is LOW XA must be stable and, on the rising edge of XWEN, XD must be valid.

Figure 4.35 shows the timing of a write to memory with two wait states.

Figure 4.35. Memory write with two wait states

Memory bank select

The XCSN chip select lines are controlled by the address of a valid transfer, and the system memory map mode. Before the system memory is remapped, the boot ROM at 0x30000000 is also mapped to the base address of 0x00000000.

Table 4.11shows the relationship between the inputs and the generated value of XCSN.

Table 4.11. XCSN coding

Input HSELExtMem

Input Remap

Input HADDR[29:28]

Output XCSN[3:0]

0

X

XX

1111

1

0

00

0111

1

0

01

1101

1

0

10

1011

1

0

11

0111

1

1

00

1110

1

1

01

1101

1

1

10

1011

1

1

11

0111

XCSN is also held in the 1111 state asynchronously during reset.

Memory write control

The 4-bit XWEN write enable signal allows the four bytes in the 32-bit wide word to be written independently. The byte assignments are:

  • XWEN[0] controls XD[7:0]

  • XWEN[1] controls XD[15:8]

  • XWEN[2] controls XD[23:16]

  • XWEN[3] controls XD[31:24].

The SMI controls XWEN for writes in word (32-bit), halfword (16-bit) and byte (8-bit) quantities. The SMI uses HSIZE[1:0] and HADDR[1:0] to select the width and order of each write to memory. This information must be valid before XWEN is asserted.

Table 4.12 shows the bytes selected according to the HSIZE and HADDR[1:0] inputs.

Table 4.12. XWEN coding

HSIZE[1:0]

HADDR[1:0]

XWEN[3:0]

10 (word)

XX

0000

01 (half word)

0X

1100

01 (half word)

1X

0011

00 (byte)

00

1110

00 (byte)

01

1101

00 (byte)

10

1011

00 (byte)

11

0111

Configurable memory access wait states

The SMI only supports global (the same for every bank) wait states for read and write accesses. This is configurable (in the HDL model, not in synthesized hardware) between zero and three waits for reads, and between two and three for writes. Figure 4.35 shows a memory transfer with two wait states. A transfer with more wait states causes more wait cycles to be added. The external address and data information remains valid until the memory access cycle is completed. For writes, the XWEN signal is extended, going LOW during the first wait, and not going HIGH until the final cycle of the transfer. Before synthesis, the wait states can be configured by altering the 2-bit wide constants READWAIT and WRITEWAIT. WRITEWAIT must be value 2 or greater.

System test access

During system TIC testing, the external bus output of the SMI is controlled by the active HIGH TicRead signal from the TIC. This is used to pass read data from the HRDATAin bus onto the external test bus XD. During normal operation this signal is held LOW.

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