4.9.3. System description

The following paragraphs give a description of how the HDL code for the module is set out. A basic system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs and outputs used in the module. This part should be read together with the HDL code.

A basic block diagram of the static memory interface system is shown in Figure 4.36.

Figure 4.36. Static memory interface module block diagram

The static memory interface module comprises the input bus registers, the wait state counter used to insert wait states, and the external memory control signal generation.

All registers used in the system are clocked from the rising edge of the system clock HCLK, and use the asynchronous reset HRESETn.

Figure 4.36 shows the static memory interface HDL file.

Figure 4.37. Static memory interface module system diagram

The main sections in the SMI module are explained in more detail in the following paragraphs:

Constant definitions

The constants READWAIT and WRITEWAIT are used to set the number of wait states that are inserted when a read and write transfer is performed. The value of zero to three for reads, and two to three for writes, is set for all transfers to all memory banks, and although configurable in the HDL code, it is permanently set when synthesized.

AHB slave bus interface

This module uses the standard AHB slave bus interface, which comprises:

  • the valid transfer detection logic

  • the address and control registers, which are used to store the information from the address phase of the transfer for use in the data phase.

The default address setting of the module is external RAM from 0x00000000 to 0x1FFFFFFF, and external boot ROM from 0x30000000 to 0x3FFFFFFF. When the Remap signal is HIGH, indicating that remapped memory is in use, external RAM is mapped from 0x00000400 to 0x1FFFFFFF, with internal memory being mapped in the first 0x000 to 0x400 region.

Wait state generation

The counter register is used to insert wait states according to the values set in the READWAIT and WRITEWAIT constants. The counter is loaded with the relevant value when a read or write transfer begins, and decrements the value until no more wait states have to be added. The counter value is used to generate the input to the HREADYout register, which is set LOW while the counter is not zero.

AHB output data bus generation

The HRDATAout output is driven to XD during a normal external memory read transfer, to propagate the read data value from the external bus onto the AHB. HRDATAout is driven LOW at all other times.

The registered HREADYout output is driven LOW while the current value of the wait state counter is not zero.

The HRESP output is held LOW, because the SMI always generates an OKAY response to all transfers.

External bus output generation

This section contains the signals that are driven onto the external bus:

  • XD is generated from either the AHB read or write data buses, depending on the current system mode of operation. HWDATAin is used during a normal external memory write transfer, and HRDATAin is used during a TIC testing read cycle. Because XD is a tristate bus, it is only driven by the SMI when the current transfer is a standard write or a TIC testing read, allowing XD to be driven by any external modules at all other times.

  • XA is driven with a registered version of bits [30:0] of HADDR, because the full system address range is not required on the external bus.

  • XCSN is generated from the input address during a valid read or write transfer. Bits [29:28] of the address are decoded as shown in Table 4‑8 on page ‑54. When Remap is LOW, the boot ROM is mapped at the base address, in addition to its standard address. External RAM access is not dependant on the Remap input. During reset, or when the memory is not addressed, all XCSN output bits are set HIGH to deselect all banks of external memory.

  • XOEN is set LOW during a valid read transfer, and is set HIGH at all other times.

  • XWEN is generated from the size and address settings for a write transfer, selecting the transfer size and byte lane to use, as shown in Table 4‑9 on page ‑55. A registered output is used to avoid the generation of glitches, which can cause incorrect values to be written to the external ROM.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential