4.10.1. Signal descriptions

The TIC has three primary interfaces:

Table 4.13 shows the TIC module signal descriptions for an AHB-based system.

Table 4.13. TIC signal descriptions for AHB

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Reset

Input

The bus reset signal is active LOW and is used to reset the system and the bus. This is the only active LOW signal.

HADDR[31:0]

Address bus

Output

The 32-bit system address bus.

HTRANS[1:0]

Transfer type

Output

Indicates the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL or IDLE. The TIC does not use the BUSY transfer type.

HWRITE

Transfer direction

Output

When HIGH this signal indicates a write transfer and when LOW a read transfer.

HSIZE[2:0]

Transfer size

Output

Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The TIC does not support larger transfer sizes.

HBURST[2:0]

Burst type

Output

Indicates if the transfer forms part of a burst. The TIC always performs incrementing bursts of unspecified length.

HPROT[3:0]

Protection control

Output

The protection control signals indicate if the transfer is an opcode fetch or data access, as well as if the transfer is a supervisor mode access or user mode access. These signals can also indicate whether the current access is cacheable or bufferable.

HWDATA[31:0]

Write data bus

Output

The write data bus is used to transfer data from the master to bus slaves during write operations. A minimum data bus width of 32 bits is recommended, however this can easily be extended to allow for higher bandwidth operation.

HREADY

Transfer done

Input

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESP[1:0]

Transfer response

Input

The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY and SPLIT.

HBUSREQtic

Bus request

Output

A signal from the TIC to the bus arbiter which indicates that it requires the bus.

HLOCKtic

Locked transfers

Output

When HIGH this signal indicates that the master requires locked access to the bus and no other master must be granted the bus until this signal is LOW.

HGRANTtic

Bus grant

Input

This signal indicates that the TIC is currently the highest priority master. Ownership of the address and control signals changes at the end of a transfer when HREADY is HIGH, so a master gains access to the bus when both HREADY and HGRANTx are HIGH.

TESTBUS

Test data bus

Input

This is the bidirectional external data bus. In normal operation it is driven by the external bus interface. During system test it becomes the test data bus and its direction is controlled by the test bus request A and B signals.

TESTREQA

Test bus request A

Input

This is the test bus request A input signal and is required as a dedicated device pin. During normal system operation the TESTREQA signal is used to request entry into the test mode. During test TESTREQA is used, in combination with TESTREQB, to indicate the type of test vector that is to be applied in the following cycle.

TESTREQB

Test bus request B

Input

During test this signal is used, in combination with TESTREQA, to indicate the type of test vector that is to be applied in the following cycle.

TESTACK

Test acknowledge

Output

The test bus acknowledge signal gives external indication that the test bus has been granted and also indicates when a test access has completed. When TESTACK is LOW the current test vector must be extended until TESTACK becomes HIGH.

TicRead

Drive out read data

Output

This signal controls the EBI to drive the current read data from HRDATA to TESTBUS.

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