4.10.2. Function and operation of module

The TIC operates as a standard AHB bus master during system test when the external test pins show that the system is required to enter test mode. In this mode, the TIC requests control of the AHB, and when granted uses the AHB to perform system tests.

Table 4.14 shows the operation of the external test pins to change the TIC mode from normal operation into test mode.

Table 4.14. Test control signals during normal operation

TESTREQA

TESTREQB

TESTACK

Description

0

-

0

Normal operation

1

-

0

Enter test mode request

-

-

1

Test mode entered

During system test the external test pins are used to control the operation of the TIC. The operation of these pins is shown in Table 4.15.

Table 4.15. Test control signals during test mode

TESTREQA

TESTREQB

TESTACK

Description

-

-

0

Current access incomplete

1

1

1

Address vector or

control vector or

turnaround vector

1

0

1

Write vector

0

1

1

Read vector

0

0

1

Exit test mode

In test mode, the internal HCLK is driven from the external TESTCLK source. This pin can be the normal clock oscillator source input or a port replacement signal. The system bus clock must not glitch when switching between normal and test mode.

On entry into test mode the TIC indicates that it has switched to the test clock input by asserting the TESTACK signal.

Test vector types

There are five types of test vector associated with the test interface:

Address vector

The address for all subsequent read and write transfers is sampled by the TIC.

Write vector

The TIC performs an AHB write cycle, using the write data currently driven onto the external data bus.

Read vector

The TIC performs an AHB read cycle, driving the read data onto the external data bus when it becomes valid.

Control vector

Internal TIC registers are set, which control the types of read and write transfers that are performed.

Turnaround vector

Used between a read cycle and a write cycle to avoid clashes on the external data bus.

The address, control and turnaround vectors are all indicated by the same value on the TESTREQA and TESTREQB signals. The following rules can be used to determine which type of vector is being applied:

  • a read vector, or burst of read vectors, is followed by two turnaround vectors

  • when a single address or control vector is applied it is an address vector

  • when multiple address and control vectors are applied they are all address vectors, apart from the last which is a control vector.

Control vectors

The control vector is used to determine the types of transfer the TIC can perform, by setting the values of the HSIZE, HPROT and HLOCK AHB master outputs.

The default TIC bus master transfer type is:

  • 32-bit transfer width, HSIZE[2:0] signifies word transfer

  • privileged system access, HPROT[3:0] signifies supervisor data access, uncacheable and unbufferable.

Bit 0 of the control vector is used to indicate if the control vector is valid. Therefore, if a control vector is applied with bit 0 LOW, the vector is ignored and does not update the control information. This mechanism allows address vectors which have bit 0 LOW to be applied for many cycles without updating the control information.

Although the default settings are sufficient for testing many embedded system designs, the control vector can be used to change the control signals of the transfer, and can also be used to determine whether the TIC must generate fixed addresses or incrementing addresses.

Table 4.16 defines the bit positions of the control vector. The control vector bit definitions are designed to be backwards compatible with earlier versions of the TIC and therefore not all of the control bits are in obvious positions.

Table 4.16. Control vector bit definitions

Bit position

Description

0

Control vector valid

1

Reserved

2

HSIZE[0]

3

HSIZE[1]

4

HLOCK

5

HPROT[0]

6

HPROT[1]

7

Address increment enable

8

Reserved

9

HPROT[2]

10

HPROT[3]

There is no mechanism to control the types of burst that the TIC can perform and only incrementing bursts of an undefined length are supported. The TIC only supports 8-bit, 16-bit and 32-bit transfers and therefore HSIZE[2] cannot be altered and is always LOW.

To support burst accesses using the test interface, the TIC can support incrementing of the bus address. The TIC increments eight address bits and the address range that can be covered by this incrementer is dependent on the size of the transfers being performed.

The control vector provides a mechanism to enable and disable the address incrementer within the TIC. This allows burst accesses to incremental addresses, as would be used for testing internal RAM. Alternatively the address increment can be disabled, such that successive accesses of a burst occur to the same address, as would be required to continually read from a single peripheral register.

The address incrementer is disabled by default and must be enabled using a control vector prior to use.

Note

The control vector is primarily used to change signals which have the same timing as the address bus. However the control vector also allows the lock signal to be changed, which is actually required before the locked transfer commences. If the HLOCK signal is used during testing it must be set a transfer before it is required. This difference in timing on the HLOCK signal can in some cases cause an additional transfer to be locked both before and after the sequence intended to be locked.

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