4.10.3. Test vector sequences

The following test vector sequences are described:

Entering test mode

In normal operating mode TESTREQA is LOW, indicating that test access is not required and the test bus is used as required for normal operation, which is usually part of the external bus interface. Entering test mode allows test vectors to be applied externally that causes transfers on the internal bus.

The following sequence, required to enter test mode, is illustrated in Figure 4.39:

  1. TESTREQA is asserted to request test bus access.

  2. Test mode is entered when the TIC has been granted the internal bus and this is indicated by the assertion of the TESTACK signal.

  3. At this point TESTCLK becomes the source of the internal HCLK signal.

  4. When test mode has been entered TESTREQB is asserted to initiate an address vector.

  5. The TIC does not perform any internal transfers until a valid address vector has been applied.

A synchronous tester would not be expected to poll TESTACK for the bus. Normally the TESTREQA signal would be asserted for a minimum number of cycles guaranteed to gain access to the bus (completion of the longest wait-state peripheral access or the maximum number of cycles for all bus masters to have completed their current instruction).

Figure 4.39. Test start sequence

Write vectors

Figure 4.40 shows the sequence of events when applying a set of write test vectors. Initially an address vector is applied and this is followed by a write test vector.

Figure 4.40. Write test vectors

The TESTREQA and TESTREQB signals are pipelined and are used to indicate what type of vector is applied in the following cycle.

Figure 4.40 shows an example of a number of write transfers being performed.

The TIC samples the address, TESTREQA, and TESTREQB signals at time T3, and following this it can initiate the appropriate transfer on the AHB. In the following cycle the write data is driven onto TESTBUS and it is then sampled on the following clock edge, T4, and driven onto the internal bus.

If the internal transfer is not able to complete, the TESTACK signal is driven LOW and this indicates that the external test vector must be applied for another cycle.

Read vectors

Read transfers are more complex because they require TESTBUS to be driven in the opposite direction, and therefore additional cycles are required to prevent bus clash when changing between different drivers of TESTBUS. Figure 4.41 shows a typical test sequence for reads.

Figure 4.41. Read test vectors

The TESTREQA and TESTREQB signals are used in the same way as for write transfer. Initially TESTREQA and TESTREQB are used to apply an address vector and then in the following cycle they are used to indicate that a read transfer is required. For the first cycle of a read TESTBUS must be tristated, which ensures that the external equipment driving TESTBUS has an entire cycle to tristate its buffers before the TIC enables the on-chip buffers to drive out the read data.

At the end of a burst of reads it is also necessary to allow time for bus turnaround. In this case the TIC must turn off the internal buffers and an entire cycle is allowed before the external test equipment starts to drive TESTBUS.

The end of a burst of reads is indicated by both TESTREQA and TESTREQB being HIGH, as for an address vector. In fact they must indicate an address vector for two cycles, which allows for the turnaround cycle at the start of the burst and also the turnaround cycle at the end of the burst.

Control vector

The operation of the TIC can be modified by the use of a control vector. Whenever more than one address vector is applied in succession, the last vector is considered to be a control vector and is not latched as the address. Bit 0 of the control vector is used to determine whether or not the control vector must be considered valid, which allows multiple address vectors to be applied without changing the control information.

Figure 4.42 shows the process of inserting a control vector.

Figure 4.42. Control vector

At time T4 the TIC can determine that TESTBUS contains a control vector. This is because the previous cycle was an address vector, and TESTREQA and TESTREQB are indicating that the following cycle is either a read or a write and therefore the current cycle must be a control vector.

Burst vector

The examples of read and write transfers shown in Figure 4.42 also show how additional transfers can be used to form burst transfers on the bus. The TIC has limited capabilities for burst transfers and can only perform undefined length incrementing bursts.

The TIC contains an 8-bit incrementer and, if an attempt is made to perform a burst which crosses the incrementer boundary, the address simply wraps and the TIC signals the transfer as NONSEQUENTIAL. The exact boundary at which this occurs is dependent on the size of the transfer. For word transfers the incrementer overflows at 1KB boundaries, for halfword transfers it overflows at 512-byte boundaries, and for byte transfers the overflow occurs at 256-byte boundaries.

Read-to-write and write-to-read transfers

It is possible to switch between read transfers and write transfers without applying a new address vector. Usually this is done with the address incrementer disabled, so that both the read transfers and the write transfers are to the same address. It is also possible to do this with the incrementer enabled if the test circumstances require it.

When moving from a read transfer to a write transfer it is also necessary to allow two cycles for bus handover and therefore TESTREQA and TESTREQB must signal an address vector for two cycles after the read. This does not cause the address to be changed unless it is followed by a third address vector.

Figure 4.43 illustrates the sequence of events.

Figure 4.43. Read vector followed by write vector

Exiting test mode

Test mode is exited using the following sequence:

  1. Apply a single cycle of address vector, which causes an IDLE cycle internally. This ensures any internal transfers have been completed and an ADDRESS-ONLY transfer is performed on the internal bus.

  2. TESTREQA and TESTREQB are both driven LOW to indicate that test mode is to be exited.

  3. When the test interface has been configured for normal system operation, TESTACK goes LOW to indicate that test mode has been exited.

It is important that test mode can be entered and exited cleanly so that the TIC can be used for diagnostic test during system operation, as well as during production testing.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A