4.10.4. System description

This describes how the HDL code for the TIC is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This should be read together with the HDL code.

Figure 4.44 shows the TIC module block diagram.

Figure 4.44. TIC module block diagram

The TIC comprises two state machines, which are used to control the access to the AHB of the master interface, and the application of test vectors from the external bus to the system.

All registers in the system are clocked from the rising edge of the system clock HCLK, and use the asynchronous reset HRESETn.

A diagram of the TIC HDL file is shown in Figure 4.45.

Figure 4.45. TIC module system diagram

The main sections of the code are explained in the following paragraphs:

Granted state machine

This is part of the standard AHB bus master interface, and is used to determine when the TIC is granted the bus, and when it can drive the address, control and data outputs.

The state machine is shown in Figure 4.46, and only advances when the HREADY input is set HIGH.

Figure 4.46. TIC module granted state machine

TIC vector state machine

This section of the code is used to control the application of test vectors from the external tester onto the AHB.

Figure 4.47 illustrates the operation of the TIC vector state machine.

Figure 4.47. TIC vector state machine

At reset the TIC is in the IDLE state and does not request use of the AHB. When in the IDLE state TESTACK is driven LOW to indicate that the test interface cannot be used.

The TESTACK signal controls all transactions around the state machine, except for the transition from IDLE to START. In all other cases the state machine remains in the same state if the TESTACK signal is low.

The TESTREQA signal moves from the IDLE state to the START state. The state of TESTREQB is not checked when moving from normal operation to test mode.

In some system implementations it is necessary to switch from an internal clock source to an external clock TESTCLK which is used during test mode. When TESTREQA first goes HIGH this can be used as an indication that the clock source must be changed. A return signal that indicates when the clock switch has occurred successfully can be used to prevent the move into the START state until the test clock is in use.

If clock switching is being used, it is possible that TESTREQA is asynchronous to the on-chip clock before test mode is entered. Therefore a synchronizer is used to generate a synchronized version of TESTREQA to control the movement from the IDLE state to the START state.

The START state ensures that the first vector applied is an address vector to prevent read and write vectors occurring before the address has been initialized. The START state is only exited when TESTREQA and TESTREQB indicate an address vector and the following state is ADDRVEC.

In the ADDRVEC state the TIC registers the address on the TESTBUS. The ADDRVEC state is used for both address and control vectors, so additional logic is required to determine whether the value on TESTBUS must be considered as an address or as a control vector. If the previous cycle was an address vector and the following cycle (as indicated by TESTREQA and TESTREQB) is not an address vector, the current cycle is a control vector.

It is possible to stay in the ADDRVEC state for a number of cycles, but usually an address vector is followed by either read or write transfers.

If a write transfer is being performed, the TIC moves into the WRITEVEC state at the same time that it initiates the transfer on the bus. Multiple write transfers can be performed by remaining in the WRITEVEC state. Usually the WRITEVEC is followed by an address vector. However, it is also possible to move directly to a read transfer by moving to the READVEC state.

When a read, or a burst of reads is performed, the TIC enters the READVEC state. This state indicates that the TIC is starting a read transfer on the bus and it is not until the following cycle that the read data appears. When the READVEC state is first entered the TESTBUS is tristated, but becomes driven during additional cycles in the READVEC state.

All read vectors must be followed by two turnaround vectors. For the first of these cycles the TIC moves into the LASTREAD state, during which the last read of the transfer completes and is driven out on to the external TESTBUS. During the LASTREAD state no internal transfers are started and the TIC performs IDLE transfers on the bus.

Following the LASTREAD state the TIC moves into the TURNAROUND state, during which time the external TESTBUS is tristated. The TURNAROUND state is usually followed by an address vector, but it is also possible to go immediately to a write vector or another read.

The usual method to exit from test is to return to the ADDRVEC state and then set both TESTREQA and TESTREQB LOW to return to IDLE and effectively exit from test. In fact, at any point the test mode can be exited by setting both TESTREQA and TESTREQB LOW, and eventually this causes the TIC to exit from test.


When applying TIC vectors it is theoretically possible to assert the HLOCK output and then exit from the test. If this happens and then the TIC is granted the bus under normal operation, it effectively locks up the bus. No protection is provided within the TIC to prevent this occurrence.

AHB address generation

There are four main sources of the HADDR output in the TIC:

  • current address registers

  • previous address registers

  • external data bus

  • incrementer.

The current address is held during a standard read or write cycle, because the address loaded during the previous address vector is used for all subsequent read and write transfers.

The previous address is only used when a split or retry response has been generated by the currently selected slave, and the TIC is set in incrementing mode. When the transfer is regenerated, the incremented address has moved on for the next transfer, so the previous address must be stored for use.

When an address vector is applied, the TIC must read in the new address from the external data bus TESTBUS. This new value is stored in the iHADDR registers, and used for the following read and write transfers.

If address incrementing is enabled, sequential read and write vectors increments the address according to the transfer size that has been set. The first read or write transfer after an address vector is to that address, subsequent transfers have their address incremented. This continues until a control vector is used to disable address incrementing.

Sequential incrementing read and write vectors are signalled as SEQUENTIAL transfers on the AHB, but a NONSEQUENTIAL transfer is added when the address incrementer crosses an 8-bit boundary, set by the current transfer size.

Control vector detection

This part is used to detect a control vector, and contains the control registers. A control vector is the last address vector in a burst of addresses, so is only detected when TESTREQA and TESTREQB indicate that the next transfer is a read or write vector, and there have been two or more address vectors. The TIC vector state machine is used to detect this, when LastVect and CurrentVect are set to address vector, and NextVect is either a read or a write vector. Also, bit 0 of the control vector (on TESTBUS) must be set HIGH for it to be valid, allowing for bursts of addresses.

When it has been detected, the control vector is written to the registers used to hold the transfer settings for HSIZE, HLOCK, HPROT, and if address incrementing is enabled. These values are then held until the next control vector is detected and stored.

Read data control

TicRead is used to enable the EBI to drive the current read data value from HRDATA onto TESTBUS. It is set HIGH when the last vector was a read, allowing time for the read data to be driven onto the AHB. This output is disabled when the TIC is not granted control of the bus, allowing the EBI to function normally.

Split or retry detection

The TIC must know when the currently selected slave has generated a split or retry, and this section is used to detect that response. If the TIC loses grant before the transfer has been regenerated, the value of the SplitRetry signal is held until the TIC has gained control of the bus again.

SR1 and SR2 are also used to indicate the first and second cycles of a SPLIT/RETRY response. SR2 is registered to remove a combinational path from HRESP to HTRANS.

AHB bus master output signal generation

Because the TIC is an AHB bus master, it must drive all of the output signals needed to control the operation of AHB slaves on the bus, and also the bus grant request output. This section generates these outputs, and controls when they can be driven out.

HTRANS is generated according to the granted state machine, the TIC vector state machine, the split or retry status, and the incrementer boundary condition.

NONSEQUENTIAL transfers are generated:

  • during a read or write following an address

  • during a read or write when the TIC has just gained control of the bus

  • during a regenerated read or write that has been split or retried

  • when the address incrementer has crossed an 8-bit boundary during a sequential read or write.

SEQUENTIAL transfers are generated in incrementing mode:

  • when a read follows a read or a write

  • when a write follows a write.

IDLE transfers are generated at all other times, because no bus transfers have to be performed.

HWRITE is set HIGH when the current transfer is a write, and is set LOW at all other times. During a regenerated split/retry transfer, the last vector is used.

HBUSREQtic is set LOW when the TIC vector state machine is in the IDLE state, and is set HIGH at all other times, because the bus is only requested when test mode has been entered.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A