5.1.1. Hardware interface and signal description

The interrupt controller module is connected to the APB bus. Table 5.1 shows the signal descriptions for the interrupt controller.

Table 5.1. APB signal descriptions for interrupt controller

Signal

Type

Direction

Description

PCLK

Peripheral clock

Input

This clock times all bus transfers. Both the LOW phase and HIGH phase of PCLK are used to control transfers.

PRESETn

Peripheral reset

Input

The bus reset signal is active LOW and is used to reset the system.

PENABLE

Peripheral enable

Input

This enable signal is used to time all accesses on the peripheral bus.

PSELIC

Peripheral slave select

Input

When HIGH, this signal indicates that this module has been selected by the APB bridge. This selection is a decode of the system address bus.

PADDR[8:2]

Peripheral address

Input

This is the peripheral address bus, which is used for decoding register accesses. The addresses become valid before PENABLE goes HIGH and remains valid after PENABLE goes LOW.

PWRITE

Peripheral transfer direction

Input

This signal indicates a write when HIGH and a read when LOW. It has the same timing as the peripheral address bus.

PWDATA[5:0]

Peripheral write data bus

Input

The write peripheral data bus is driven by the bridge at all times.

PRDATA[7:0]

Peripheral read data bus

Output

The read peripheral data bus is driven by this block during read cycles (when PWRITE is LOW and PSELIC is HIGH).

FIQESource

FIQ interrupt source

Input

FIQ interrupt signal into the interrupt module. This active HIGH signal indicates that a fast interrupt request has been generated.

IRQESource[0]

IRQESource[7:2]

IRQ interrupt sources

Input

IRQ interrupt signals into the interrupt module. These active HIGH signals indicate that interrupt requests have been generated. (IRQESource[1] is internally generated in the interrupt controller module and is used to provide a software triggered IRQ.)

nFIQ

FIQ output

Output

Active LOW fast interrupt request input to the ARM core.

nIRQ

IRQ output

Output

Active LOW interrupt request input to the ARM core.

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