5.1.2. Function and operation of the interrupt controller module

The interrupt controller provides a simple software interface to the interrupt system. Certain interrupt bits are defined for the basic functionality required in any system. The remaining bits are available for use by other devices in any particular implementation. In an ARM system, two levels of interrupt are available:

Ideally, in an ARM system, only a single FIQ source is in use at any particular time. This provides a true low-latency interrupt, because a single source ensures that the interrupt service routine can be executed directly without the requirement to determine the source of the interrupt. It also reduces the interrupt latency because the extra banked registers, which are available for FIQ interrupts, can be used to maximum efficiency by preventing the requirement for a context save.

Separate interrupt controllers are used for FIQ and IRQ. Only a single bit position is defined for FIQ, which is intended for use by a single interrupt source, while up to 32 bits are available in the IRQ controller. The standard configuration only makes eight interrupt request lines available. This can be extended to up to 32 sources by altering the IRQSize constant setting and increasing the width of the PWDATA and PRDATA lines to the interrupt controller.

The IRQ interrupt controller uses a bit position for each different interrupt source. Bit positions are defined for a software-programmed interrupt, a communications channel, and counter-timers. Bit 0 is unassigned in the IRQ controller so that it can share the same interrupt source as the FIQ controller.

All interrupt source inputs must be active HIGH and level-sensitive. Any inversion or latching required to provide edge sensitivity must be provided at the generating source of the interrupt.

No hardware priority scheme nor any form of interrupt vectoring is provided, because these functions can be provided in software.

A programmed interrupt register is also provided to generate an interrupt under software control. Typically this can be used to downgrade an FIQ interrupt to an IRQ interrupt.

Interrupt control

The interrupt controller provides:

  • interrupt status

  • raw interrupt status

  • an enable register.

The enable register is used to determine whether or not an active interrupt source must generate an interrupt request to the processor.

The raw interrupt status indicates whether or not the appropriate interrupt source is active prior to masking and the interrupt status indicates whether or not the interrupt source is causing a processor interrupt.

The enable register has a dual mechanism for setting and clearing the enable bits. This allows enable bits to be set or cleared independently, with no knowledge of the other bits in the enable register.

When writing to the enable set location, each data bit that is HIGH sets the corresponding bit in the enable register. All other bits of the enable register are unaffected. Conversely, the enable clear location is used to clear bits in the enable register while leaving other bits unaffected.

Figure 5.2 shows the structure for a single segment of the interrupt controller.

Figure 5.2. Single bit slice of the interrupt controller

The IRQ controller usually has a larger number of bit slices, where the exact size is dependent on the system implementation.

The FIQ interrupt controller consists of a single bit slice, located on bit 0.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential