5.1.3. Register memory map

The base address of the interrupt controller is not fixed and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed. Table 5.2 shows the register memory map.

Table 5.2. Register memory map of the interrupt controller APB peripheral

Address

Read location

Write location

IntBase + 0x000

IRQStatus

-

IntBase + 0x004

IRQRawStatus

-

IntBase + 0x008

IRQEnable

IRQEnableSet

IntBase + 0x00C

-

IRQEnableClear

IntBase + 0x010

-

IRQSoft

IntBase + 0x100

FIQStatus

-

IntBase + 0x104

FIQRawStatus

-

IntBase + 0x108

FIQEnable

FIQEnableSet

IntBase + 0x10C

-

FIQEnableClear

IntBase + 0x014

IRQTestSource

IRQTestSource

IntBase + 0x018

IRQSourceSel

IRQSourceSel

IntBase + 0x114

FIQTestSource

FIQTestSource

IntBase + 0x118

FIQSourceSel

FIQSourceSel

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