5.1.4. Register descriptions

The following registers are provided for both FIQ and IRQ interrupt controllers:

Enable

Read-only. The enable register is used to mask the interrupt input sources and defines which active sources generate an interrupt request to the processor. This register is read-only, and its value can only be changed by the enable set and enable clear locations. If certain bits within the interrupt controller are not implemented, the corresponding bits in the enable register must be read as undefined.

An enable bit value of 1 indicates that the interrupt is enabled and allows an interrupt request to reach the processor. An enable bit value of 0 indicates that the interrupt is disabled. On reset, all interrupts are disabled.

EnableSet

Write-only. This location is used to set bits in the interrupt enable register. When writing to this location, each data bit that is HIGH causes the corresponding bit in the enable register to be set. Data bits that are LOW have no effect on the corresponding bit in the enable register.

EnableClear

Write-only. This location is used to clear bits in the interrupt enable register. When writing to this register, each data bit that is HIGH causes the corresponding bit in the enable register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the interrupt enable register.

RawStatus

Read-only. This location provides the status of the interrupt sources to the interrupt controller. A HIGH bit indicates that the appropriate interrupt request is active prior to masking.

Status

Read-only. This location provides the status of the interrupt sources after masking. A HIGH bit indicates that the interrupt is active and generates an interrupt to the processor.

Soft

Write only. A write to bit 1 of this register sets or clears a programmed interrupt. Writing to this register with bit 1 set HIGH generates a programmed interrupt, while writing to it with bit 1 set LOW clears the programmed interrupt. The value of this register can be determined by reading bit 1 of the source Status register. Bit 0 of this register is not used.

Two extra read/write registers are defined for both FIQ and IRQ to allow testing of the interrupt controller module using the AMBA test methodology. They must not be accessed during normal operation.

TestSource

Same size as RawStatus, and used to load RawStatus with test data.

SourceSel

1-bit wide (bit 0). When set, the value in TestSource is multiplexed into RawStatus.

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