5.1.5. Standard configuration of registers

The FIQ interrupt controller is one bit wide and is located on bit 0. The source of this interrupt is implementation-dependent.

The interrupt controller is customized to fit into each application. The following is an example minimum set of interrupt bits assigned in a system:

Table 5.3 gives a typical example allocation of IRQ sources.

Table 5.3. Example of IRQ sources

Bit

Interrupt source

0

Undefined

1

Programmed Interrupt

2

Comms Rx

3

Comms Tx

4

Timer 1

5

Timer 2

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