5.1.6. System description

This section describes how the HDL code for the interrupt controller is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of all the registers, inputs and outputs used in the system. This section should be read together with the HDL code.

Figure 5.3 shows the interrupt controller module block diagram.

Figure 5.3. Interrupt controller module block diagram

The interrupt controller comprises sets of interrupt registers and test registers that are used to control the generation of the two interrupt outputs to the ARM core, based on the interrupt inputs.

All registers used in the system are clocked from the rising edge of the system clock PCLK, and use the asynchronous reset PRESETn.

Two diagrams are used to show the interrupt controller HDL file. Figure 5.4 shows the layout of the bit slices that are used for bit 0 of the FIQ and bits 0 and [5:2] of the IRQ.

Figure 5.4. Interrupt controller slice system diagram

Figure 5.5 shows the layout of the whole system.

Figure 5.5. Interrupt controller module system diagram

The main sections in this module are explained in more detail in the following paragraphs:

Constant definitions

The first two constants that are specified (IRQSIZE and FIQSIZE), are used to set the number of IRQ and FIQ lines that are used in the system. The defaults are for eight IRQ lines and one FIQ line. These constants must only be changed when the number of interrupt input sources are changed.

The other constants are used to set the relative addresses of the interrupt controller registers from the base address.

IRQ generation

Figure 5.4 shows the structure of the IRQ generation logic from the external interrupt sources.

The read/write TestSource register is used to hold the test value. This is passed through a multiplexor, and then used to switch between the external and internal test interrupt sources. This is the read-only RawStatus value, which is gated with the output of the enable register, and used to generate the Status output.

All of the IRQ sources are then combined to generate the active LOW nIRQ output, which is set LOW when any of the IRQ lines are set HIGH.

FIQ generation

The FIQ logic is similar to the IRQ logic, but in the default system is only one bit wide, and does not have a software programmable source. The nFIQ output is directly generated from the single interrupt source bit, using an inverter.

Output data generation

This section is used to decode the current address during a read, and generate the correct data to be driven onto the APB data bus. The address is compared with all of the register addresses, and the value of PRDATANext is set accordingly. This is then stored in the iPRDATA register to help decrease the output propagation time by using a registered output, rather than an output with the combinational delay of the large multiplexor. This register also synchronizes the reading of all raw interrupt inputs to the rising edge of the clock. The PRDATA output is then driven by the register.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential