5.2.1. Signal descriptions

Figure 5.4Table 5.4 describes the APB signals used and produced by the remap and pause controller.

Table 5.4. APB signal descriptions for remap and pause controller

Signal

Type

Direction

Description

PCLK

Peripheral clock

Input

This clock times all bus transfers. Both the LOW phase and HIGH phase of PCLK are used to control transfers.

PRESETn

Peripheral reset

Input

The bus reset signal is active LOW and is used to reset the system.

PENABLE

Peripheral enable

Input

This enable signal is used to time all accesses on the peripheral bus.

PSELRPC

Peripheral slave select

Input

When HIGH, this signal indicates that this module has been selected by the APB bridge. This selection is a decode of the system address bus.

PADDR[5:2]

Peripheral address bus

Input

This is the peripheral address bus, which is used for decoding register accesses. The addresses become valid before PENABLE goes HIGH and remains valid after PENABLE goes LOW.

PWRITE

Peripheral transfer direction

Input

This signal indicates a write when HIGH and a read when LOW.

It has the same timing as the peripheral address bus.

PWDATA[7:0]

Peripheral write data bus

Input

The write peripheral data bus is driven by the bridge at all times.

PRDATA[7:0]

Peripheral read data bus

Output

The read peripheral data bus is driven by this block during read cycles (when PWRITE is LOW and PSELRPC is HIGH).

nFIQ

FIQ output

Input

FIQ interrupt input from the interrupt controller.

nIRQ

IRQ output

Input

IRQ interrupt input from the interrupt controller.

Pause

Pause mode

Output

HIGH when in the wait for interrupt pause mode, and LOW at all other times.

Remap

Reset memory map

Output

LOW when the reset memory map is in use, and HIGH when the normal memory map is in use.

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