5.2.4.  Remap and pause register descriptions

Pause

Write-only. Writing to the pause location causes the system to enter a wait for interrupt state, by setting the Pause output HIGH.

The exact effect of writing to this location is not defined, but typically this would prevent the processor from fetching more instructions until the receipt of an interrupt or a power-on reset. More registers can be added to provide more sophisticated power-saving modes.

Identification

Read-only. The identification location provides identification information about the system. Only a single-bit implementation (bit 0) is required, which is used to indicate if there is more ID information:

0 = no more ID information 1 = more ID information is available.

If bit zero of the identification register is set, more bits are required to provide more detailed system identification information.

ClearResetMap

Write-only. Writing to the clear reset memory map location changes the system memory map. It changes from that required during boot-up to that required during normal operation. This is done by setting the Remap output to HIGH. When the reset memory map has been cleared and the normal memory map is in use, there is no method of resuming the reset memory map, other than undergoing a power-on reset condition. A typical system implementation is to map the system ROM to location 0x00000000 at reset, but to change the memory map after reset, such that RAM is located at location 0x00000000 for normal operation. In a system where such remapping does not occur, writing to this register has no effect.

ResetStatus

Read-only. The reset status location provides the reset status. Only one bit of this register is defined in this specification and this is bit 0, which provides the power-on reset status. Further bits in the ResetStatus register can be implemented to provide more detailed reset information. The ResetStatus register has a dual mechanism for setting and clearing bits, allowing independent bits to be altered with no knowledge of the other bits in the register. This is done by using the ResetStatusClear and the ResetStatusSet registers.

The single bit defined in this specification is the power-on reset bit, which can be used to determine if the most recent reset was caused by initial power-on, or if a warm reset has occurred:

0 = no POR since flag was last cleared 1 = POR.

ResetStatusClear

Write-only. This location is used to clear reset status flags. When writing to this register each data bit that is HIGH causes the corresponding bit in the ResetStatus register to be cleared. Data bits that are LOW have no effect on the corresponding bit in the ResetStatus register.

ResetStatusSet

Write-only. This location is used to set reset status flags. When writing to this register each data bit that is HIGH causes the corresponding bit in the ResetStatus register to be set. Data bits that are LOW have no effect on the corresponding bit in the ResetStatus register. The power-on reset status bit (bit 0) cannot be set by software, because it can only be set during a system reset. The extra bits of the register are included in the specification to ensure the reset status functionality can easily be expanded.

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