5.2.5. System description

The following paragraphs describe how the HDL code for the remap and pause controller module is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of all the registers, inputs and outputs used in the system. This section should be read together with the HDL code.

A basic block diagram of the remap and pause controller module is shown in Figure 5.7.

Figure 5.7. Remap and pause module block diagram

The remap and pause controller comprises registers to generate the Remap and Pause outputs, and logic to allow the reading of the identification and reset status values.

All registers used in the system are clocked from the rising edge of the system clock PCLK, and use the asynchronous reset PRESETn. The Pause register also uses the two interrupt inputs as asynchronous resets, allowing the value to be cleared while the system is not clocked.

A diagram of the remap and pause HDL file is shown in Figure 5.8.

Figure 5.8. Remap and pause module system diagram

The main sections in this module are explained in more detail in the following sections:

Constant definitions

The constant IDENTIFICATION holds the identification information about the system. The default setting for this value is all zero. The maximum size for this value is the width of the read and write data buses of the module.

ResetStatus value generation

This register is modified through the ResetStatusSet and ResetStatusClear addresses. When writing to the set location, each data bit that is HIGH sets the corresponding bit in the ResetStatus register. All other bits of the register are unaffected. Each data bit that is set HIGH when writing to the clear location clears the corresponding bit in the ResetStatus register, leaving all other bits unaffected.

The power-on-reset bit (bit 0) cannot be set by writing to the set location, because it is only set HIGH during system reset. It can be cleared in the same way as the other register bits.

Pause output generation

A register is used to hold the wait for interrupt state value. The Pause output is synchronously set HIGH (on the rising edge of PCLK) when the Pause location is written to, with any value, and is asynchronously set LOW by PRESETn, nFIQ or nIRQ. When set HIGH, it can only be set LOW with a reset or an interrupt.

Figure 5.9 shows the operation of setting and clearing the Pause registered output.

Figure 5.9. Pause signal timing

Remap output generation

This register is used to hold the system memory map state value. The Remap output is set LOW on reset, indicating that the reset memory map is in use. It is set HIGH when the ClearResetMap location is written to with any value, indicating that the normal system memory map is in use. When set HIGH, it can only be set LOW by a system reset.

Output data generation

This section is used to decode the current address during a read, and generate the correct data to be driven onto the APB read data bus. The address is compared with all of the register addresses, and the value of PRDATANext is set accordingly. This is then stored in the iPRDATA register to help decrease the output propagation time by using a registered output, rather than an output with the combinational delay of the large multiplexor. The PRDATA output is then driven by the register.

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