5.3.1. Signal descriptions

The two sets of signals associated with the timers module are:

The signal descriptions for the timers module are listed in Table 5.6.

Table 5.6. APB signal descriptions for timer

Signal

Type

Direction

Description

PCLK

Peripheral clock

Input

This clock times all bus transfers. Both the LOW phase and HIGH phase of PCLK are used to control transfers.

PRESETn

Peripheral reset

Input

The bus reset signal is active LOW and is used to reset the system.

PENABLE

Peripheral enable

Input

This enable signal is used to time all accesses on the peripheral bus.

PSELCT

Peripheral slave select

Input

When HIGH, this signal indicates that this module has been selected by the APB bridge. This selection is a decode of the system address bus.

PADDR[5:2]

Peripheral address bus

Input

This is the peripheral address bus, which is used for decoding register accesses. The addresses become valid before PENABLE goes HIGH and remains valid after PENABLE goes LOW.

PWRITE

Peripheral transfer direction

Input

This signal indicates a write when HIGH and a read when LOW. It has the same timing as the peripheral address bus.

PWDATA[15:0]

Peripheral write data bus

Input

The write peripheral data bus is driven by the bridge at all times.

PRDATA[15:0]

Peripheral read data bus

Output

The read peripheral data bus is driven by this block during read cycles (when PWRITE is LOW and PSELCT is HIGH).

INTCT

Counter 1 interrupt

Output

Active HIGH interrupt signal to the interrupt controller module. This signal indicates an interrupt has been generated by counter 1 having been decremented to zero.

INTCT2

Counter 2 interrupt

Output

Active HIGH interrupt signal to the interrupt controller module. This signal indicates an interrupt has been generated by counter 2 having been decremented to zero.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential