5.3.3. Timer operation

The timer is loaded by writing to the Load register and, if enabled, counts down to zero. When zero is reached, an interrupt is generated. The interrupt can be cleared by writing to the Clear register.

After reaching a zero count, if the timer is operating in free-running mode it continues to decrement from its maximum value. If periodic timer mode is selected, the timer reloads the count value from the Load register and continues to decrement. In this mode the counter effectively generates a periodic interrupt. The mode is selected by a bit in the Control register.

At any point, the current counter value can be read from the Value register.

The counter is enabled by a bit in the Control register. At reset, the counter is disabled, the interrupt is cleared, and the Load register is set to zero. The mode and prescale values are set to free-running, and clock divide of one respectively.

Figure 5.11 is a block diagram showing timer operation.

Figure 5.11. Timer operation

The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the fol-lowing:

Figure 5.12 shows how the timer clock frequency is selected in the prescale unit.

Figure 5.12. Prescale clock enable generation

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A