5.3.4. Register memory map

The base address of the timers module is not fixed and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

Table 5.7. Memory map of the time APB peripheral

Address

Read location

Write location

TimerBase + 0x00

Timer1Load

Timer1Load

TimerBase + 0x04

Timer1Value

-

TimerBase + 0x08

Timer1Control

Timer1Control

TimerBase + 0x0C

-

Timer1Clear

TimerBase + 0x20

Timer2Load

Timer2Load

TimerBase + 0x24

Timer2Value

-

TimerBase + 0x28

Timer2Control

Timer2Control

TimerBase + 0x2C

-

Timer2Clear

TimerBase + 0x10

Timer1Test

Timer1Test

TimerBase + 0x30

Timer2Test

Timer2Test

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