5.3.5. Timer register descriptions


Read/write. This register contains the initial value to be loaded into the counter and is also used as the reload value in periodic mode. This register is the same width as the counter (default is 16 bits).


Read-only. This location gives the current value of the counter.


Write-only. Writing to this location clears an interrupt generated by the counter.


Read/write. This register provides enable/disable, mode and prescale configurations for the counter.

Figure 5.13 shows the control register.

Figure 5.13. The control register


Two special registers are provided for validation purposes, Timer1Test and Timer2Test. These locations must not be accessed during normal system operation.

Both registers are read/write and are 2 bits wide, as shown in Table 5.8.

Table 5.8. Test register bit functions






Counter test mode



Test clock select

The counter test mode bit is stored in a register in both FRCs. The test clock select bit is stored in a single register in the top-level timers module, but can be accessed from either test address.

When the counter test mode bit is set, the selected 16-bit counter is divided into four separate 4-bit counters that continually loop round from 15 to 0. This reduces the testing time needed to ensure that the correct counting sequence is performed. Clearing this bit (default) brings the selected timer back to normal operation.

When the test clock select bit is set in either of the two test registers, a special test clock (NOT PENABLE ANDed with PSELCT) is fed into the prescale unit instead of the system clock (therefore both counters have to be using the same clock source, either normal or test). Clearing this bit (default) selects the system clock as the prescale clock input (normal operation).

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