5.3.6. System description

This section describes how the HDL code for the timers module is set out. A basic system block diagram, with information about the main parts of the HDL code, is followed by details of all the registers, inputs and outputs used in this module. This should be read together with the HDL code.

A basic block diagram of the timers module is shown in Figure 5.14.

Figure 5.14. Timers module block diagram

The timers module comprises two 16-bit programmable free-running counters, and clock prescale enable generation logic. The free-running counters comprise four linked 4-bit counters, interrupt generation logic and counter control registers.

All registers used in the system are clocked from the rising edge of the system clock PCLK and use the asynchronous reset PRESETN.

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