5.3.7. Timer system description

A diagram of the timers module HDL file is shown in Figure 5.15.

Figure 5.15. Timers module system diagram

The main sections in this module are explained in the following paragraphs:

Address decoder

This section is used to generate the TestSel signal, which is used to indicate an access to either of the test registers, and the Frcsel select lines to the FRCs based on the current address. Because there are two instantiations (in the default system) of an identical FRC module, part of the address decoding must be done at the previous system level.

Test clock select generation

This register is used to store the current value of bit 1 of all counter test registers. A read or write to any of the test register addresses access this single register.

Clock prescaler

The 8-bit prescale registers are used to generate the two prescale signals of divide by 16 and divide by 256, by decrementing the current value of the registers. The enable signal PreScaleEn is used to control the operation of the registers, which by default is always set, but in test clock mode is a combination of PENABLE and PSELCT, allowing an output clock pulse to be generated for each read or write access to the timers module.

Output clock enable generation

The three different clock enable signals (equivalent to the system clock, the system clock divided by 16, and the system clock divided by 256) enable the timer clocks in the two FRC modules, based on the amount of prescale that is required.

Figure 5.16 and Figure 5.17 show the timing of these enable signals.

Figure 5.16. Timer module counter enable timing - system clock selected

Figure 5.17. Timer module counter enable timing - test clock selected

Output data generation

This section is used to decode the current address during a read, and generate the correct data to be driven onto the APB read data bus. The address is compared with all of the register addresses, and the value of PRDATANext is set accordingly. This is then stored in the iPRDATA register to help decrease the output propagation time by using a registered output, rather than an output with the combinational delay of the large multiplexor. The PRDATA output is then driven by the register.

The read data is based on the FRC data outputs, with the local Test Clock Select register output also used when reading from a test location.

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