5.3.9. FRC signal descriptions

Table 5.9 shows descriptions for the FRC signals.

Table 5.9. Signal descriptions for FRC

Signal

Type

Direction

Description

PCLK

Peripheral clock

Input

Direct connection from timers module.

PRESETn

Peripheral reset

Input

Direct connection from timers module.

PENABLE

Peripheral enable

Input

Direct connection from timers module.

PADDR[4:2]

Peripheral address

Input

Direct connection from timers module.

PWRITE

Peripheral transfer

direction

Input

Direct connection from timers module.

PWDATA[15:0]

Peripheral write

data bus

Input

Direct connection from timers module.

Frcsel

FRC register select

Input

FRC register select, driven HIGH when a register in this FRC is addressed. There is a select line for each counter in the timers module.

Enable0

Enable prescale 0

Input

Counter clock enable, divide by 1.

Enable1

Enable prescale 4

Input

Counter clock enable, divide by 16.

Enable2

Enable prescale 8

Output

Counter clock enable, divide by 256.

Intfrc

Interrupt output

Output

Interrupt output from the counter, generated when 16-bit counter reaches zero. There is an interrupt output for each counter in the timers module.

Dataout

Read data output

Output

Read data output used to generate PRDATA for register reads. There is a read data output for each counter in the timers module.

Figure 5.19 shows the FRC HDL file.

Figure 5.19. FRC module system diagram

The main sections in this module are described in:

Control, Test and Load registers

The Control, Test (bit zero only) and Load registers only change when written to, and hold their values at all other times.

Counter enable selection

The enable input to use is selected according to the prescale mode setting in the control registers. The selected input is then used to generate an internal enable, which is also gated with the enable bit of the control registers. An additional signal ensures that the load data value is clocked into the counters when a load operation is performed.

16-bit counter

The counter is split up into four 4-bit parts (nibbles) to allow efficient testing. Each nibble is used to generate a carry signal (when the 4-bit counter overflows), which is passed to the next nibble as an enable. When Counter Test Mode is selected, all carry enable signals are set HIGH, forcing all four nibbles to count at the same time.

The 16-bit counter value is stored in registers, which are enabled using the externally generated counter enable. The input to the registers is normally the output from the four 4-bit decrementers, but when a new value is written to the Load registers, or when the counter reaches zero and periodic mode is set, the current value of the Load registers is stored in the counter registers.

The operation of the counter is shown in Figure 5.20.

Figure 5.20. FRC module count down diagram

Interrupt generation

An interrupt is generated when the full 16-bit counter reaches zero, and is only cleared when the TimerClear location is written to. A register is used to hold the value until the interrupt is cleared. The most significant carry bit of the counter is used to detect the counter reaching zero.

Output data generation

The current address is used to generate the internal read data value for the Test, Load, Value and Control locations. Because the Test and Control registers are not 16-bits, the read values are padded out with the Load register value, minimizing the number of output changes when different registers are read.

This read data value is then passed to the timers module, and then driven onto the APB read data bus.

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