5.4.3. System description

The following paragraphs give a description of how the HDL code for the peripheral to bridge multiplexor is set out. A simple system block diagram, with information about the main parts of the HDL code, is followed by details of the registers, inputs, and outputs used in the module. This part should be read together with the HDL code.

Figure 5.22 shows the peripheral to bridge module block diagram.

Figure 5.22. Peripheral to bridge multiplexor module block diagram

The peripheral to bridge multiplexor module is comprised of a set of multiplexors for the slave read data.

A diagram of the peripheral to bridge multiplexor HDL file is shown in Figure 5.23.

Figure 5.23. Peripheral to bridge multiplexor module system diagram

To allow the use of case statements for the multiplexors, the PSEL slave select inputs are combined to create a multi-bit bus signal. This bus is then used as the select control on the read data multiplexor.

One input to the PRDATA multiplexor is tied LOW, so that when no peripheral slaves are selected, no read data appears on PRDATA.

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