6.3.1. AHB signal descriptions

Table 6.5 shows signal descriptions for the AHB internal RAM module

Table 6.5. Signal descriptions for the AHB internal RAM module

Signal

Type

Direction

Description

HCLK

Bus clock

Input

This clock times all bus transfers.

HRESETn

Reset

Input

The bus reset signal is active LOW, and is used to reset the system and the bus.

HADDR[31:0]

Address bus

Input

The 32-bit system address bus.

HTRANS[1:0]

Transfer type

Input

Indicated the type of the current transfer, which can be NONSEQUENTIAL, SEQUENTIAL, IDLE or BUSY.

HWRITE

Transfer direction

Input

When HIGH this signal indicates a write transfer, and when LOW, a read transfer.

HSIZE[2:0]

Transfer size

Input

Indicates the size of the transfer, which is typically byte (8-bit), halfword (16-bit) or word (32-bit). The protocol allows for larger transfer sizes up to a maximum of 1024 bits.

HWDATA[31:0]

Write data bus

Input

The write data bus is used to transfer data from the master to the bus slaves during write operations. A minimum data bus width of 32 bits is recommended. However, this can easily be extended to allow for higher bandwidth operation.

HSELIntMem

Slave select

Input

Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

HRDATA[31:0]

Read data bus

Output

The read data bus is used to transfer data from bus slaves to the bus master during read operations. A minimum data bus width of 32 bits is recommended. However, this can easily be extended to allow for higher bandwidth operation.

HREADYin

HREADYout

Transfer done

Input / output

When HIGH the HREADY signal indicates that a transfer has finished on the bus. This signal can be driven LOW to extend a transfer.

HRESP[1:0]

Transfer response

Output

The transfer response provides additional information on the status of a transfer. This module always generates the OKAY response.

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