6.3.3. Function and operation of module

Operations described are:

Memory initialization from local data file

On simulation initialization, the internal RAM module loads in data from the file specified in the FileName setting. This must be stored as an 8-character Verilog $readmemh format data file (for both VHDL and Verilog format models), which cannot contain more data than the model supports. Address lines (starting with @) and single line comments (starting with //) are valid, but all other non-value characters are not allowed. Loading starts from address zero, and continues incrementing on word boundaries until an address line is found in the file. Loading then continues from that address. All values are initialized to zero before loading is started. An example intram.dat file is shown in Example 6.3.

Example 6.3. 

ea00000b
ea000005
// Data values stored at 0x00000200
@00000200
01234567
89ABCDEF

The internal RAM module stores data as 32-bit words, and in default configuration is 256 words deep, which is equivalent to 1KB. This is only accessible when the normal memory map is in use (Remap set HIGH), and occupies the address range from 0x00000000 to 0x000003FF. If the size of the internal memory is modified, the address range that it occupies also changes. This requires the system decoder to be updated so that it only selects the internal RAM module over the correct address range.

Memory read and write from system bus

The internal RAM module is accessed by standard system bus transfers, allowing both reads from memory and writes to memory. These can be performed as 32-bit word, 16-bit halfword or 8-bit byte transfers. Each byte lane of the transfer is treated separately, so a byte write to byte zero does not alter the values stored in the other three bytes at that word address. Data reads are all treated the same, and the full 32-bit word at the selected word address is driven out onto the system data bus.

All transfers are performed with zero wait states. An ERROR response is never generated.

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