6.4.1. Signal descriptions

Table 6.7 shows signal descriptions for the Ticbox module

Table 6.7. Signal descriptions for the Ticbox module

Signal

Type

Direction

Description

TESTCLK

Test mode clock

Input

This is the system clock HCLK in test mode. All the test interface transactions are timed using this signal.

nReset

External reset

Input

Active LOW external reset input. Used to control the operation of the Ticbox module.

TESTREQA

Test request A

Output

Indicates test vector mode. See the test interface chapter in the AMBA Specification for more information about the test protocol. It is driven early in the LOW phase of TESTCLK and held to the falling edge of TESTCLK.

TESTREQB

Test request B

Output

Indicates test vector mode. See the test interface chapter of the AMBA Specification for more information about the test protocol. It is driven early in the LOW phase of TESTCLK and held to the falling edge of TESTCLK.

TESTACK

Test acknowledge

Input

Indicates that the test bus has been granted and also that a test access has been completed.

TESTBUS[31:0]

Test data bus

Input/ output

32-bit bidirectional test port.

Copyright © 2001 ARM Limited. All rights reserved.ARM DDI 0226A
Non-Confidential