6.4.3. Function and operation of module

When the external system reset input has been deasserted, the Ticbox requests access to the system. This is done by asserting TESTREQA HIGH and TESTREQB LOW. The Test Interface Controller (TIC) then indicates when test mode has been entered by asserting TESTACK HIGH. When in test mode, the test input file is then read and translated by the Ticbox into AMBA test interface transactions, using the TESTREQA and TESTREQB signals.

The Ticbox applies test vectors to the system every time the TESTACK line indicates the system is ready. On read cycles the value is masked and then compared with the masked expected value given in the test vector file. An error message is given if the comparison fails. System testing ends when the end of the input vector file is reached, and the Ticbox indicates this by asserting both TESTREQA and TESTREQB LOW to end the simulation.

A typical simulation output display while running a TIC program is shown in Example 6.4.

Example 6.4. 

#    Time: 2603 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Addressing location 80000614

#    Time: 2703 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Writing data 00000005

#    Time: 3003 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Addressing location 80000618

#    Time: 3103 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Reading. Expected: 00000010. Mask 0000003F

#    Time: 3403 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Addressing location 8000061c

#    Time: 3703 ns Iteration: 0 Instance:/u_ticbox
# ** Warning: Error on vector read. Expected: 00000010 Actual: 00000011 Mask: 0000003F
#    Time: 3753 ns Iteration: 0 Instance:/u_ticbox

#    Time: 4003 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Addressing location 80000584

#    Time: 4303 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Writing data 00000000

#    Time: 4603 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Addressing cycle at end

#    Time: 4903 ns Iteration: 0 Instance:/u_ticbox
# ** Note: ; Exiting Test Mode

#    Time: 5203 ns Iteration: 0 Instance:/u_ticbox
# ** Failure: Vector run completed: halting simulation
#    Time: 77703 ns Iteration: 0 Instance:/u_ticbox
# Break at ticbox.vhd line 288

In Example 6.4, a read error has occurred, but the error message is broadcast later in the simulation. This is because there are a number of clock cycles between when the read is requested, and when the information is sampled by the Ticbox to be compared with the expected value. The example simulation has been run without HaltOnMismatch set, and therefore the program does not stop after the error has been detected. Verbosity is set, because all TIF vector comments have been displayed in the simulation output.

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