6.4.10. SIM format file

The Verilog Ticbox requires the input file to be in the SIM format, which is formatted as a Verilog `include input file, with each test vector calling a task in the Verilog Ticbox behavioural module.

A SIM file is generated from a TIF file using the conversion script tif2sim in the following way:

tif2sim infile.tif > infile.sim

Comments use the Verilog style double slash (//) and, because of the properties of Verilog `include files, are not displayed in the simulation output. The Verilog Ticbox directly generates the simulation comments based on the test vector that is being run.

The TIF file above is shown in Example 6.7 in SIM format:

Example 6.7. 

// Addressing location 84000000 
A(32'h84000000);

// Writing data 55555555 
W(32'h55555555);

// Addressing location 84000008 
A(32'h84000008);

// Writing data 000000C0 
W(32'h000000C0);

// Addressing location 84000004 
A(32'h84000004);

// Reading. Expected: 55555547. Mask: 0000FFFF 
R(32'h55555547, 32'h0000FFFF);
A(32'hZZZZZZZZ);

// Addressing location 84000000 
A(32'h84000000);

// Writing data DADADADA 
W(32'hDADADADA);

// Reading. Expected: DADADADA. Mask: 0000FFFF 
R(32'hDADADADA, 32'h0000FFFF);

// Reading. Expected: 000000C0. Mask: 000000CC 
R(32'h000000C0, 32'h000000CC);
A(32'hZZZZZZZZ);

// Addressing location 84000004 
A(32'h84000004);

// Reading. Expected: AAAAAAB8. Mask: 00000000 
R(32'hAAAAAAB8, 32'h00000000);
A(32'hZZZZZZZZ);

// Writing data 000000C4 
W(32'h000000C4);

// Writing data 12345678 
W(32'h12345678);

// Looping for 5 cycles 
L(32'd5);

// Addressing cycle at end 
A(32'h00000000);

// Exiting Test Mode 
E(32'hZZZZZZZZ);

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