6.5.1. Signal descriptions

Table 6.9 shows signal descriptions for the tube module.

Table 6.9. Signal descriptions for the tube module

Signal

Type

Direction

Description

XD[31:0]

External data

Input

This is the external data bus, which is sampled by this module during write transfers.

XCSN[3:0]

External chip select

Input

These signals are active LOW chip enables.

XWEN[3:0]

External write enable

Input

This is the active LOW memory write enable. For little-endian systems, XWEN[0] controls writes to the least significant byte and XWEN[3], the most significant. The example system is configured to be little-endian.

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