| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| Non-Confidential | |
 PDF version | |
| Home > Debugging Your System > Disabling EmbeddedICE-RT |
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You can disable EmbeddedICE-RT in two ways:
By wiring the DBGEN input LOW.
When DBGEN is LOW:
DBGBREAK and DBGRQ are ignored by the core
DBGACK is forced LOW by the ARM720T core
interrupts pass through to the processor uninhibited
the EmbeddedICE-RT logic enters low-power mode.
Hard-wiring the DBGEN input LOW permanently disables debug state information. However, you must not rely on this for system security.
By setting bit 5 in the Debug Control Register (described in Debug control register). Bit 5 is also known as the EmbeddedICE-RT disable bit.
You must set bit 5 before doing either of the following:
programming breakpoint or watchpoint registers
changing bit 4 of the Debug Control Register.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| Non-Confidential | |
| PDF version | |
| Home > Debugging Your System > Disabling EmbeddedICE-RT |