If the system is in halt mode, any of the following types of interrupt force the processor into debug state:

You can use the EmbeddedICE-RT logic to program the conditions under which a breakpoint or watchpoint can occur. Alternatively, you can use the DBGBREAK signal to enable external logic to flag breakpoints or watchpoints and monitor the following:

The timing is the same for externally‑generated breakpoints and watchpoints. Data must always be valid around the rising edge of HCLK. When this data is an instruction to be breakpointed, the DBGBREAK signal must be HIGH around the rising edge of HCLK. Similarly, when the data is for a load or store, asserting DBGBREAK around the rising edge of HCLK marks the data as watchpointed.

When a breakpoint or watchpoint is generated, there might be a delay before the ARM720T core enters debug state. When it enters debug state, the DBGACK signal is asserted. The timing for an externally‑generated breakpoint is shown in Figure 9.3.