| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
 PDF version | |
| Home > Programmer’s Model > Exceptions > Exception vectors |
| |||
| Home > Programmer’s Model > Exceptions > Exception vectors | |||
The ARM720T processor can have exception vectors mapped to either low or high addresses, controlled by the V bit in the Control Register of the system control coprocessor (See Control Register). Table 2.4 shows the exception vector addresses.
Table 2.4. Exception vector addresses
| High address | Low address | Exception | Mode on entry |
|---|---|---|---|
|
| Reset | Supervisor |
|
| Undefined instruction | Undefined |
|
| Software interrupt | Supervisor |
|
| Abort (prefetch) | Abort |
|
| Abort (data) | Abort |
|
| Reserved | Reserved |
|
| IRQ | IRQ |
|
| FIQ | FIQ |
The low addresses are the defaults.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Exception vectors |