| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
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An abort indicates that the current memory access cannot be completed. It can be signaled either by the protection unit, or by the HRESP bus. The ARM720T processor checks for the abort exception during memory access cycles.
There are two types of abort, as follows:
This occurs during an instruction prefetch. The prefetched instruction is marked as invalid, but the exception is not taken until the instruction reaches the head of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place.
This occurs during a data access. The action taken depends on the instruction type:
Single data transfer instructions
(LDR, STR) write-back modified
base registers. The Abort handler must be aware of this.
The swap instruction (SWP) is
aborted as though it had not been executed.
Block data transfer instructions (LDM, STM)
complete. If write-back is set, the base is updated. If the instruction attempts
to overwrite the base with data (that is, it has the base in the
transfer list), the overwriting is prevented. All register overwriting
is prevented after an abort is indicated. This means, in particular,
that r15 (always the last register to be transferred) is preserved
in an aborted LDM instruction.
After fixing the reason for the abort, the handler must execute the following irrespective of the processor state (ARM or Thumb):
SUBS PC, r14_abt, #4 for a Prefetch Abort
SUBS PC, r14_abt, #8 for a Data Abort
This restores both the PC and the CPSR, and retries the abortedinstruction.
There are restrictions on the use of the external abort signal.See External aborts.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Programmer’s Model > Exceptions > Abort |