ARM720T™ Technical Reference Manual 2.8.1. Action on entering an exception

2.8.1. Action on entering an exception

When handling an exception, the ARM720T processor behaves as follows:

It preserves the address of the next instruction in the appropriate LR.
1. If the exception has been entered from ARM state, the address of the next instruction is copied into the LR (that is, current PC+4 or PC+8 depending on the exception). See Table 2.3 for details).
2. If the exception has been entered from Thumb state, the value written into the LR is the current PC, offset by a value so that the program resumes from the correct place on return from the exception. This means that the exception handler does not have to determine which state the exception was entered from.
For example, in the case of SWI:
```
MOVS PC, r14_svc 
```
always returns to the next instruction regardless of whether the SWI was executed in ARM or Thumb state.
It copies the CPSR into the appropriate SPSR.
It forces the CPSR mode bits to a value that depends on the exception.
It forces the PC to fetch the next instruction from the relevant exception vector.

It can also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.

If the processor is in Thumb state when an exception occurs, it automatically switches into ARM state when the PC is loaded with the exception vector address.

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