ARM720T™ Technical Reference ManualRevision: r4p3
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2.8.3. Exception entry and exit summary

Table 2.3 summarizes the PC value preserved in the relevant r14 register on exception entry, and the recommended instruction for exiting the exception handler.

Table 2.3. Exception entry and exit

Exception

Return instruction

Previous state

  

ARM r14_x

Thumb r14_x

BL[1]

MOV PC, r14

PC + 4

PC + 2

SWIa

MOVS PC, r14_svc

PC + 4

PC + 2

UDEFa

MOVS PC, r14_und

PC + 4

PC + 2

FIQ[2]

SUBS PC, r14_fiq, #4

PC + 4

PC + 4

IRQb

SUBS PC, r14_irq, #4

PC + 4

PC + 4

PABTa

SUBS PC, r14_abt, #4

PC + 4

PC + 4

DABT[3]

SUBS PC, r14_abt, #8

PC + 8

PC + 8

RESET[4]

NA

-

-

[1] PC is the address of the BL,

SWI, Undefined Instruction, or Fetch, that had the Prefetch Abort.

[2] PC is the address of the instruction that was not executed because the FIQ or IRQ took priority.

[3] PC is the address of the Load or Store instruction that generated the Data Abort.

[4] The value saved in r14_svc upon reset is Unpredictable.

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