Only bit 0 of this 32 bit read/write register is used. It determines whether an abort exception entry was caused by a breakpoint, a watchpoint, or a real abort. The format is shown in Figure 9.14.

Bit 0 is set when the ARM720T core takes a Prefetch or Data Abort as a result of a breakpoint or watchpoint. If, on a particular instruction or data fetch, both the Debug Abort and the external Abort signal are asserted, the external Abort takes priority, and the DbgAbt bit is not set. Once set, DbgAbt remains set until reset by the user. The register is accessed by MRC and MCR instructions.