Writing to CP15 Register 8 controls the Translation Lookaside Buffer (TLB). The ARM720T processor implements a unified instruction and data TLB.

Two TLB operations are defined. The function to be performed is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 Register 8.

The TLB operations and the instructions that you can use are shown in Table 3.3.

MCR p15, 0, <Rd>, c8, c5, 0

MCR p15, 0, <Rd>, c8, c6, 0

MCR p15, 0, <Rd>, c8, c7, 0

MCR p15, 0, <Rd>, c8, c5, 1

MCR p15, 0, <Rd>, c8, c6, 1

MCR p15, 0, <Rd>, c8, c7, 1

In the instructions shown in Table 3.3, c7 is the preferred value for the CRn field, because it indicates a unified MMU.

Reading from CP15 Register 8 is undefined.

The Invalidate TLB single entry function invalidates any TLB entry corresponding to the Modified Virtual Address (MVA) given in Rd.