| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
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| Home > Instruction and Data Cache > IDC enable, disable, and reset |
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The IDC is automatically disabled and flushed on HRESETn. When enabled, cachable read accesses cause lines to be placed in the cache.
To enable the IDC:
Make sure that the MMU is enabled first by setting bit 0 in the Control Register.
Enable the IDC by setting bit 2 in the Control Register. The MMU and IDC can be enabled simultaneously with a single write to the Control Register.
To disable the IDC:
Clear bit 2 in the Control Register.
Perform a flush by writing to the cache operations register.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Instruction and Data Cache > IDC enable, disable, and reset |