Abandons the executing instruction.

Flushes the cache and Translation Lookaside Buffer (TLB).

Disables the Write Buffer (WB), cache, and MMU.

Resets the FCSE PID.

Continues to fetch instructions from incrementing word addresses.

Overwrites r14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of the saved PC and SPSR is not defined.

Forces M[4:0] to b10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR T bit.

Forces the PC to fetch the next instruction from the reset exception vector. Exception vectors are located at either high or low addresses depending on the state of the V bit in CP15 register 1 (LOW = low addresses, HIGH = high addresses).

Resumes execution in ARM state.