ARM720T™ Technical Reference ManualRevision: r4p3
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A.1. AMBA interface signals

The AMBA interface signals are shown in Table A.1.

Table A.1. AMBA interface signals

Signal nameTypeDescription
HCLKInputBus clock. This is the only clock on the ARM720T processor.
HADDR[31:0]Output32-bit system address bus.
HTRANS[1:0]OutputIndicates type of current transfer.
HBURST[2:0]OutputIndicates burst length of current transfer.
HWRITEOutputIndicates direction of current transfer.
HSIZE[2:0]OutputIndicates size of current transfer.
HPROT[3:0]OutputProtection control signals
HGRANTInputBus transfer granted.
HREADYInputIndicates that the current transfer has finished.
HRESP[1:0]InputIndicates transfer status.
HWDATA[31:0]OutputWrite data bus.
HRDATA[31:0]InputRead data bus.
HBUSREQOutputBus transfer request.
HLOCKOutputIndicates locked access.
HCLKENInputBus clock enable.
HRESETnInputGlobal reset.
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