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The instruction set for the ARM720T processor enables you to implement specialized additional instructions using coprocessors. These are separate processing units that are coupled to the ARM720T processor, although CP15 is built into the ARM720T processor.
The CP15 register map might change in future ARM processors. You are strongly recommended to structure software so that any code accessing CP15 is contained in a single module, enabling it to be easily updated.
You can only access CP15 registers with MRC and MCR instructions in a privileged mode. The instruction bit pattern of the MRC and MCR instructions is shown in Figure 3.1.
CDP, LDC, and STC instructions, as well as unprivileged.
MRC and MCR instructions to CP15 cause the Undefined Instruction trap to be taken.
The CRn field of MRC and MCR instructions specifies the coprocessor register to access. The CRm field and opcode_2 fields specify a particular action when addressing some registers.
In all instructions accessing CP15:
the opcode_1 field Should Be Zero (SBZ)
the opcode_2 and CRm fields Should Be Zero except when accessing registers 7, 8, and 13 when the specified values must be used to select the desired cache, TLB, or process identifier operations.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Configuration > Internal coprocessor instructions |