ARM720T™ Technical Reference Manual 3.3.2. Control Register

3.3.2. Control Register

Reading from CP15 Register 1 reads the control bits. The CRm and opcode_2 fields Should Be Zero when reading CP15 Register 1. Control Register read format is shown in Figure 3.4.

Figure 3.4. Control Register read format

Writing to CP15 Register 1 sets the control bits. The CRm and opcode_2 fields Should Be Zero when writing to CP15 Register 1. Control Register write format is shown in Figure 3.5.

Figure 3.5. Control Register write format

With the exception of the V bit, all defined control bits are set to zero on reset. The control bits have the following functions:

M Bit 0

MMU enable/disable:

0 = MMU disabled

1 = MMU enabled.

A Bit 1

Alignment fault enable/disable:

0 = Address Alignment Fault Checking disabled

1 = Address Alignment Fault Checking enabled.

C Bit 2

Cache enable/disable:

0 = Instruction and/or Data Cache (IDC) disabled

1 = Instruction and/or Data Cache (IDC) enabled.

W Bit 3

Write buffer enable/disable:

0 = Write Buffer disabled

1 = Write Buffer enabled.

P Bit 4

When read, returns 1. When written, is ignored.

D Bit 5

When read, returns 1. When written, is ignored.

L Bit 6

When read, returns 1. When written, is ignored.

B Bit 7

Big-endian/little-endian:

0 = Little-endian operation

1 = Big-endian operation.

S Bit 8

System protection: Modifies the MMU protection system.

R Bit 9

ROM protection: Modifies the MMU protection system.

Bits 12:10

When read, this returns an Unpredictable value. When written, it Should Be Zero, or a value read from these bits on the same processor.

Note

Using a read-write-modify sequence when modifying this register provides the greatest future compatibility.

V Bit 13

Location of exception vectors:

0 = low addresses

1 = high addresses.

The value of the V bit reflects the state of the VINITHI external input, sampled while HRESETn is LOW.

Bits 31:14

When read, this returns an Unpredictable value. When written, it Should Be Zero, or a value read from these bits on the same processor.

Enabling the MMU

You must take care if the translated address differs from the untranslated address, because the instructions following the enabling of the MMU are fetched using no address translation. Enabling the MMU can be considered as a branch with delayed execution.

A similar situation occurs when the MMU is disabled. The correct code sequence for enabling and disabling the MMU is given Interaction of the MMU and cache.

Note

When the MMU is disabled the Cache is disabled.
If the cache and write buffer are enabled when the MMU is not enabled, the results are Unpredictable.

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