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Reading CP15 Register 5 returns the value of the Fault Status Register (FSR). The FSR contains the source of the last fault.
Only the bottom 9 bits are returned. The upper 23 bits are Unpredictable.
The FSR indicates the domain and type of access being attempted when an abort occurred:
This is always read as zero. Bit 8 is ignored on writes.
These specify which of the 16 domains (D15-D0) was being accessed when a fault occurred.
These indicate the type of access being attempted.
The encoding of these bits is shown in Fault address and fault status registers. The FAR is only updated on data faults. There is no update on prefetch faults.
Writing to CP15 Register 5 sets the FSR to the value of the data written. This is useful when a debugger has to restore the value of the FSR. The upper 24 bits written Should Be Zero.
The CRm and opcode_2 fields Should Be Zero when reading or writing CP15 Register 5. Fault Status Register format is shown in Figure 3.8.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Configuration > Registers > Fault Status Register |