| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
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Writing to CP15 Register 7 manages the unified instruction and data cache of the ARM720T. Only one cache operation is defined using the following opcode_2 and CRm fields in the MCR instruction that writes the CP15 Register 7.
The Invalidate ID cache function invalidates all cache data. Use this with caution.
Register 7 is shown in Table 3.2.
Table 3.2. Cache operation
Function | opcode_2 value | CRm value | Data | Instruction |
|---|---|---|---|---|
Invalidate ID cache | b000 | b0111 | SBZ |
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Reading from CP15 Register 7 is undefined.
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Configuration > Registers > Cache Operations Register |