| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
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The ARM720T contains an 8KB mixed Instruction and Data Cache (IDC).
The cache comprises four segments of 64 lines each, each line containing eight words. The IDC is always reloaded a line at a time. The IDC is enabled or disabled using the ARM720T Control Register and is disabled on HRESETn.
The MMU must never be disabled when the cache is on. However, you can enable the two devices simultaneously with a single write to the Control Register (see Control Register).
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > Instruction and Data Cache > About the instruction and data cache > IDC operation |