The C bit determines if data being read can be placed in the
IDC and used for subsequent read operations. Typically, main memory
is marked as cachable to improve system performance, and I/O space
is marked as noncachable to stop the data being stored in the ARM720T cache.
For example, if the processor is polling a hardware flag in
I/O space, it is important that the processor is forced to read
data from the external peripheral, and not a copy of the initial
data held in the cache. The cachable bit can be configured for both
pages and sections.
A line fetch of eight words is performed when a cache miss
occurs in a cachable area of memory, and it is randomly placed in
a cache bank.
Note
Memory aborts are not supported on cache line fetches and
are ignored.
An external memory access is performed and the cache is not
written.
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