| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
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An AHB transfer comprises the following:
This lasts only a single cycle. The address cannot be extended, so all slaves must sample the address during the address phase.
This phase can be extended using the HREADY signal. When LOW, HREADY causes wait states to be inserted into the transfer and enables extra time for a slave to provide or sample data.
A write data bus is used to move data from the master to a slave.
A read data bus is used to move data from a slave to the master.
Figure 6.1 shows a transfer with no wait states (this is the simplest type of transfer).
A granted bus master starts an AHB transfer by driving the address and control signals. These signals provide the following information about the transfer:
address
direction
width of the transfer
whether the transfer forms part of a burst
the type of burst.
A burst is a series of transfers. The ARM720T processor performs the following types of burst:
Incrementing burst of unspecified length.
8-beat incrementing burst only used during linefill.
Incrementing bursts do not wrap at address boundaries. The address of each transfer in the burst is an increment of the address of the previous transfer in the burst.
For more information, see Address and control signals.
For a complete description of the AHB transfer mechanism, see the AMBA Specification (Rev 2.0).
| Copyright © 2001, 2003, 2004 ARM Limited. All rights reserved. | ARM DDI 0229C |
| PDF version | |
| Home > The Bus Interface > About the bus interface > Summary of the AHB transfer mechanism |